To reduce power consumption of a semiconductor device, a tunnel FET (TFET) is attracting attention for its high controllability of current at small gate voltage (its small sub-threshold coefficient). For example, a conventional TFET includes, between a source diffusion layer of a first conductivity type and a drain diffusion layer of a second conductivity type, a impurity semiconductor layer of the second conductivity type called pocket layer (or pocket region) to contact the source diffusion layer, and includes a p-n junction plane serving as a tunnel junction plane between the source diffusion layer and the pocket layer. Examples of such TFET include a horizontal TFET in which the pocket layer is in contact with a side surface of the source diffusion layer, and a vertical TFET in which the pocket layer is formed between an upper surface of the source diffusion layer and a lower surface of a gate insulator. The vertical TFET has an advantage that its sub-threshold coefficient is smaller than that of the horizontal TFET, but has a disadvantage that the tunnel junction plane having an abrupt change in impurity concentration is difficult to form by ion implantation. Moreover, although epitaxial growth can be used to form the tunnel junction plane of the vertical TFET to exhibit an abrupt change in impurity concentration, the abruptness would be lost because impurities in the source diffusion layer and the pocket layer are diffused in a subsequent heating process.